This invention relates to a logical delaying/advancing circuit to perform fine adjustments of time accuracy, and to an electronic device such as an electronic clock that uses the logical delaying/advancing circuit to achieve high time accuracy.
Conventionally, a circuit as shown in FIG. 9 has been employed to carry out a method to perform logical delaying/advancing in units of one period of a frequency-division circuit, in order to compensate for a deviation in an oscillating of an oscillater 501 frequency resulting from a variation caused by manufacture. The logical delaying/advancing operation will be briefly explained on the basis of FIG. 9 and FIG. 10 showing a timing chart. A reference clock a outputted from a quartz oscillator circuit 501 is inputted to a frequency-dividing circuit constituted by T-type flip-flops (hereinafter called TFF) 502-509, and sequentially frequency-divided. Where no logical delaying/advancing operation is performed, accurate 1/2 frequency-division is made as in a section from time period A to time period B in FIG. 10. Terminals 511-514 of an IC are connected to D1-D4 as logical delaying/advancing data signals, and the data signals D1-D4 are pulled up by a resistance. OR gates 521-524 having inputs of VCWX as a logical delaying/advancing control signal and D1-D4 as logical delaying/advancing data signals have an output connected to a set input SX of TFFs 503-506.
The logical delaying/advancing operation is usually executed every period of 10 seconds, and at this time an "L" level of a pulse signal VCWX is generated in synchronism with a rise in the TFF 507Q output at timing B in FIG. 10. The signal VCWX has a pulse width of a half of a period of the reference clock. A predetermined TFF among the TFFs 502-506 is forcibly preset by this "L"-level pulse signal VCWX, thereby carrying out a predetermined amount of a logical delaying/advancing operation. For example, where the IC terminals 512-514 are open by virtus of pattern cutting during circuit board manufacture and the IC terminal 511 is connected to VSS in the circuit-board pattern, logical delaying/advancing data signals have D2-D4 becoming "H" and D1 becoming "L". In synchronism with the signal VCWX, output signals c, d, e and f of the OR gates 521-524 are outputted at respective levels of "L", "H", "H" and "H". Accordingly, an "L"-level pulse signal is applied to the set input SX of the TFF 503 in this case, and the Q output of the TFF 503 is forcibly brought into an "H" level (timing B). Since the frequency-divided clock of the TFF 502 is successively inputted to the TFF 503, TFF 503 has a rising Q output signal at timing c of FIG. 10, and thereafter the usual 1/2 frequency division is performed.
This series of operations act to omit one "L"-level section in the Q output of the TFF 503, that is, one period of time of the frequency-division clock of the TFF 502. If observed with respect to timing of a rise of the Q output of TFF 506, the one that would inherently rise at timing E in FIG. 10 has resulted in rising at timing D in FIG. 10. Therefore, delaying/advancing is made, as a result, in an advancing direction by one period of the Q output of the TFF 502.
It has been known perform logical delaying/advancing in a delaying or advancing direction by appropriately controlling the state of a frequency-dividing circuit at predetermined timing as described above.
In the conventional logical delaying/advancing method, the amount of delaying/advancing is determined by performing a pattern cutting of a circuit board or before at factory-shipping time of signal lines prepared as logical delaying/advancing data input means.
Therefore, where adjusting a delaying/advancing amount for a secondary temperature characteristic for a quartz rate, there is a necessity of preparing an delaying/advancing-amount adjusting means to compensate for temperature change within an IC. However, there is a difference in semiconductor processes between that of a temperature-change detecting IC and that of a logic IC, so that adjustment has to be made on the semiconductor process, raising a from the aspect problem of high cost and long development time.